1. Field of the Invention
The present invention relates generally to a noise elimination circuit, and in particular, to an improved noise elimination circuit which can eliminate all noise of a reset signal of a microprocessor or an input signal effective in a specific logic level.
2. Description of the Background Art
FIG. 1 is a circuit diagram illustrating a conventional noise elimination circuit.
Referring to FIG. 1, the conventional noise elimination circuit includes: an inverter INV1 receiving a reset bar signal /RESET, and outputting an inverted signal to a node Nd1; a noise elimination unit 10 receiving the signal transmitted to the node Nd1, for eliminating noise of the signal, and outputting the resultant signal to a node Nd2; a NOR gate NOR1 NORing the signals of the nodes Nd1, Nd2; an AND gate AND1 ANDing the signals of the nodes Nd1, Nd2; and an RS latch circuit unit 12 receiving the output signal from the NOR gate NOR1 as a set signal and the output signal from the AND gate AND1 as a reset signal, and generating a chip reset signal to an output terminal Q.
In the conventional noise elimination circuit, when the reset bar signal /RESET is enabled in a low level, the signal of the node Nd1 is transited to a high level by the inverter INV1. The signal of the node Nd1 (high) outputs a high level signal to the node Nd2 through the noise elimination unit 10 after a delay time t1. Accordingly, the reset input of the RS latch circuit unit 12 is enabled in a high level, thus clearing the RS latch circuit unit 12.
Here, the noise elimination unit 10 eliminates noise of the reset bar signal /RESET, so that an unwanted chip reset signal cannot be generated due to noise in the signal.
FIG. 2A is a circuit diagram illustrating a noise elimination unit using the R-C delay shown in FIG. 1, and FIG. 2B is a circuit diagram illustrating a noise elimination unit using an inverter and capacitor delay shown in FIG. 1.
As illustrated in FIG. 2A, the conventional noise elimination unit 10 includes: an inverter INV2 and a resistor R1 connected in series between the nodes Nd1, Nd3; a capacitor C1 connected between the node Nd3 and the ground voltage Vss; a resistor R2 connected between the nodes Nd3, Nd4; a capacitor C2 connected between the node Nd4 and the ground voltage Vss; a resistor R3 connected between the nodes Nd4, Nd5; a capacitor C3 connected between the node Nd5 and the ground voltage Vss; and an inverter INV3 connected between the nodes Nd5, Nd2.
As depicted in FIG. 2B, the conventional noise elimination unit 10 using the inverter and capacitor delay includes: an inverter INV4 connected between the nodes Nd1, Nd6; a capacitor C4 connected between the node Nd6 and the ground voltage Vss; an inverter INV5 connected between the nodes Nd6, Nd7; a capacitor C5 connected between the node Nd7 and the ground voltage Vss; an inverter INV6 connected between the nodes Nd7, Nd8; a capacitor C6 connected between the node Nd8 and the ground voltage Vss; and an inverter INV7 connected between the nodes Nd8, Nd2.
The operation of the conventional noise elimination unit 10 will now be explained.
When the signal of the node Nd1 is inputted to the noise elimination unit 10, the signal is outputted to the node Nd2 without noise after a predetermined delay time t1 in the noise elimination unit 10. That is, when the signal of the node Nd1 has a smaller noise period than the delay time t1, the noise elimination unit 10 filters the signal to prevent influence of the noise on the signal of the node Nd2.
Accordingly, the reset input signal of the RS latch circuit unit 12 (FIG. 1) has a low level, and thus the output signal Q is maintained as it is.
However, the conventional noise elimination circuit has a disadvantage in that when noise is consecutively generated before the delay time, the noise elimination unit does not successfully eliminate noise.
The problem of the conventional noise elimination circuit will now be explained with reference to FIGS. 3A and 3B.
Referring to FIG. 3A, when noise t2-t4 is consecutively inputted to the reset bar signal /RESET after the delay time t1, the signals of the nodes Nd3, Nd4, Nd5 of the noise elimination unit 10 gradually reduce the corresponding potential levels. As shown in FIG. 3A(f), the signal outputted to the node Nd2 through the inverter INV3 has an undesirable high level, as shown by the spike.
The high level signal of the node Nd2 converts the reset input signal of the RS latch circuit unit 12 into a high level signal, and thus converts the output signal Q into a high level signal. That is, the chip reset signal is generated due to unwanted noise, which causes a mis-operation of the circuit.
As illustrated in FIG. 3B, when noise t5-t6 is consecutively inputted to the reset bar signal /RESET after the delay time t1, the signals of the nodes Nd6, Nd7, Nd8 of the noise elimination unit 10 gradually reduce the corresponding potential levels. As shown in FIG. 3B(f), the signal outputted to the node Nd2 through the inverter INV7 has an undesirable high level.
The high level signal of the node Nd2 converts the reset input signal of the RS latch circuit unit 12 into a high level signal. Therefore, the chip reset signal is generated due to unwanted noise, thereby causing a mis-operation of the circuit.
Accordingly, it is an object of the present invention to provide a noise elimination circuit that can eliminate all noise of a reset signal of a microprocessor or an input signal effective in a specific logic level, by varying a filtering time through a ring oscillator and a frequency division circuit.
In order to achieve the above-described object of the present invention, there is provided a noise elimination circuit including: a ring oscillator unit for receiving first and second signals and generating a pulse signal according to the first signal, and stopping generation of the pulse signal when the first and the second signals have a first potential level; and a frequency division unit for receiving an output signal of the ring oscillator unit and then, N times frequency-dividing to generate the signal to the second signal, and being reset by the first signal. When the first potential is at a logic high level, and the second potential is at a logic low level. Conversely, when the first potential is at a logic low level, and the second potential is at a logic high level.
Preferably, the ring oscillator unit includes: a third inverter for inverting a signal of the first node, and outputting the inverted signal to a third node; an OR gate for ORing the signals of the third node and the second node, and outputting the resultant signal to a fourth node; a fourth inverter for inverting a signal of a fifth node according to the signal of the fourth node; a resistor connected between the output terminal of the fourth inverter and a sixth node; fifth and sixth inverters connected in series between the sixth node and the fifth node; a capacitor connected between the fifth node and the sixth node; an NMOS transistor for discharging a signal of the sixth node into the ground voltage according to the signal of the fourth node; and seventh and eight inverters connected in series between the fifth node and the seventh node.
In addition, the frequency division of the frequency division circuit unit is dependent upon the structure and design of the ring oscillator unit.
According to another aspect of the present invention, a noise elimination circuit includes: a first inverter receiving a reset bar signal, and outputting an inverted signal to a first node; a noise elimination unit receiving the signal of the first node, eliminating all noise of the signal, and outputting the resultant signal to a second node; a second inverter inverting the signal of the first node; an AND gate ANDing the signal of the first node and the signal of the second node; and an RS latch circuit unit receiving the output signal from the second inverter as a set signal and the output signal from the AND gate as a reset signal, and generating a chip reset signal to an output terminal.
Preferably, the noise elimination unit includes: a ring oscillator unit generating a pulse signal having a predetermined period when the signal of the first node is at a first potential, stopping the operation and clearing an output signal thereof, when the signal of the second node is at the first potential; and a frequency division circuit unit frequency-dividing the output signal from the ring oscillator unit, outputting the frequency-divided signal to the second node, and being reset when the signal of the first node is at the second potential. When the first potential is at a logic high level, and the second potential is at a logic low level. Conversely, when the first potential is at a logic low level, and the second potential is at a logic high level.
Preferably, the ring oscillator unit includes: a third inverter for inverting a signal of the first node, and outputting the inverted signal to a third node; an OR gate for ORing the signals of the third node and the second node, and outputting the resultant signal to a fourth node; a fourth inverter for inverting a signal of a fifth node according to the signal of the fourth node; a resistor connected between the output terminal of the fourth inverter and a sixth node; fifth and sixth inverters connected in series between the sixth node and the fifth node; a capacitor connected between the fifth node and the sixth node; an NMOS transistor for discharging a signal of the sixth node into the ground voltage according to the signal of the fourth node; and seventh and eight inverters connected in series between the fifth node and the seventh node.
The frequency division of the frequency division circuit unit is dependent upon the design of the ring oscillator unit.